In systems of the type that transfer data it is often necessary or desirable to generate from noise corrupted data a clock signal synchronized with that data. This is often done in telecommunication systems and in magnetic data storage systems. Circuits which provide such a synchronized clock are commonly called data tracking phase locked loops.
A data tracking phase locked loop is a feedback control system which minimizes the phase error between transitions in noisy data and the transitions of a variable frequency local oscillator. The minimization is achieved by varying the frequency of the local oscillator in accordance with a measured phase error. The phase error detection portion of the loop should meet the following criteria:
1. The phase detector output should have a low content of harmonics of the clock frequency. Otherwise, excessive filtering may be required that can unduly dampen the response of the loop to rapid phase error excursions.
2 The phase detector should tolerate normally absent data pulses (i.e., logical zeros) without generating a false phase error.
In addition, it would be useful in the testing and repair of equipment employing data tracking phase locked loops if the phase error information were made available to the system itself, particularly if computer or microprocessor controlled equipment are involved. Such phase error information could serve as a figure of merit for the operation of the data transfer channel, and allow the system to monitor or even log that aspect of its own performance. This would be very useful as a diagnostic aid both in the factory and in the field.
In a digital system it would be advantageous if the phase error information were also digital. The advantage would be greater still if the manner of obtaining the phase error were inherently digital in nature so that an expensive high speed analog-to-digital conversion can be avoided. Furthermore, digital phase error information can be arithmetically manipulated by "digital filters" within the phase locked loop, giving the designer added flexibility in choosing the response characteristics of the loop.
Furthermore, it would be advantageous if the data tracking phase locked loop itself were capable of readily attaining the phase locked condition without sweeping the frequency of the local oscillator or requiring a special preamble in the data, as in some prior data tracking phase locked loops.
Accordingly, it is an object of the present invention to provide a data tracking phase locked loop that incorporates a phase detector that produces a low content of harmonics of the clock frequency.
Another object of the invention is to provide a data tracking phase locked loop that tolerates normal absence of data pulses without generating a false phase error.
Another object of the invention is to provide a data tracking phase locked loop wherein the phase error detector inherently produces a digital output.
Another object of the invention is to provide a data tracking phase locked loop that incorporates a digital filter within its feedback loop.
It is a further object of the invention to provide a data tracking phase locked loop that readily attains the phase locked condition without sweeping the local oscillator or requiring a special preamble in the data.
These objects of the invention are met by data tracking phase locked loops constructed in accordance with the following summary.
A variable frequency oscillator runs with a center frequency that is an integral multiple n times greater than the nominal frequency of the data. A counter of modulus n continuously counts the oscillations of the variable frequency oscillator, dividing the period of the phase varying data into approxiimately n parts. The value of the count is captured each time a data pulse occurs. Once the loop is in lock, if the data were to remain absolutely stable each captured value would be the same as its predecessor. As phase shifting of the data occurs the value of the captured count increases or decreases in kind. Captured counts may be first digitally filtered or used directly to drive a digital-to-analog converter, whose output is analog filtered before being used to control the variable frequency oscillator. For example, a decrease in the captured count means the data arrived sooner and causer a voltage change in the digital-to-analog converter that causes the variable frequency oscillator to operate at a higher frequency, thus tracking the shift in the phase of the data.
A phase corrected clock is easily obtained once the variable frequency oscillator tracks the phase variations in the data; one way is to produce a signal in relation to the occurrence of a particular bit or particular count in the counter.
The loop is readily placed in phase lock by briefly operating it in a rapid phase error acquisition mode wherein the counter is set to n/2 each time a data pulse is received. During this mode of operation the loop becomes a frequency loop that approximates the behavior of a phase locked loop.
Since the output of the digital-to-analog converter is stable except when there is a change in the value of a captured count, and since the digital-to-analog converter quickly stabilizes following such changes, the detected phase error represented by the output of the digital-to-analog converter is low in harmonics of the clock frequency.
Since the counter has a modulus of n it simply "rolls over" and begins counting anew if a data pulse is absent; the previous captured count remains unaltered and no false phase error is generated.
Since the phase error originates as a count captured from a counter, the digital phase error information is inherently digital.
Since digital phase error information is readily available it may be digitally filtered before being used to control the variable frequency oscillator via the digital-to-analog converter.
Since the behavior of this circuit as a frequency loop approximates that of a phase locked loop, briefly operating the data tracking loop in a frequency loop mode before entering the phase locked mode readily allows the loop to attain the phase locked condition without sweeping the local oscillator or employing a preamble in the data.